Optimum phase timing recovery in the presence of strong intersymbol interference

ABSTRACT

A data communication device with a receiver for receiving and processing incoming signal having intersymbol interference component to produce resultant signals with less interference. The processor includes a timing recovery processor for recovering a clock signal from the sample streams of the incoming signal. The recovered clock signal is also suitable for signal detection of the incoming signals under strong intersymbol interference.

RELATED APPLICATION

The present application is based upon and claims priority benefit ofprovisional application Ser. No. 60/547,313, entitled “Optimum PhaseTiming Recovery in the Presence of Strong Intersymbol Interference”,which was filed on Feb. 24, 2004.

FIELD OF THE INVENTION

The present application relates to band limited communication systemswhere timing recovery at the optimum phase is required in the presenceof strong intersymbol interference (ISI).

BACKGROUND

Timing recovery is one of the fundamental operations in digitalcommunications to recover the transmitted data. In general, digitalcommunications can be done in either baseband or passband. In the lattercase, the encoded baseband signal is further modulated to a high carrierfrequency for transmission. Examples of baseband systems include FastEthernet (100 Mb/s) and Gigabit Ethernet over copper (1 Gb/s) as definedby IEEE 802.3ab. Examples of passband communications include gigabitEthernet over fiber and wireless LAN (local area network) systems asdefined by IEEE 802.11a, 11b, and 11g.

In contrast to carrier frequency recovery in passband communications formoving the modulated signal from passband to baseband, timing recoveryregenerates a baseband clock for sampling and decoding the basebandsignal. Therefore, timing recovery is required in both passband andbaseband communications. To achieve proper decoding, timing recovery inthe receiver is required to recover the clock of the remote transmitterand to operate at a certain sampling phase to optimize the receiverperformance. Various techniques have been devised in the past for timingrecovery of remote transmitters. For example, U.S. Pat. Nos. 6,285,726;6,363,129; 6,577,689; and U.S. patent application 2003/0142687A1describe applications of timing recovery schemes. The description of thetiming recovery systems and the applications in data communicationsystems of these patent documents are incorporated by reference in theirentireties. It is to be understood that the present invention can beimplemented in data communication systems with one or more transceivershaving receivers and transmitters. Examples of applications of theinvention of the present application include IEEE 802.3 Fast Ethernet,Gigabit Ethernet over copper, and ITU-T G.991 high-speeddigital-subscriber-line (HDSL) transceiver systems.

Most clock recovery schemes use a phase lock loop (PLL). FIG. 1Aillustrates a basic timing recovery scheme involving a phase lock loop10. As shown in FIG. 1A, the typical phase lock loop 10 consists of aphase detector (PD) 12, a loop filter (LF) 14, and a voltage or currentcontrolled oscillator (VCO or ICO) 16. The purpose of the phase detector12 is to detect the phase difference between the received signal 18 andthe recovered clock signal 20 from the timing recovery mechanism. Whenthe received signal 18 has sufficient transitions and has negligibleintersymbol interference (ISI), a simple phase detector 12 that comparesthe received signal 18 transitions with the voltage or currentcontrolled oscillator output 20 can be deployed. Such schemes have beenwidely incorporated in timing recovery systems of the past. The purposeof the loop filter 14 is to reduce jitter from a signal 22 from a phasedetector 12 to generate a signal 24 whose steady state value can operatethe voltage or current controlled oscillator 16 at a frequency equal tothat of the received baseband signal.

As also shown in FIG. 1A, once the clock is properly recovered by thephase lock loop 10, it can be fed to an analog-to-digital converter(ADC) 26 to drive the sampling of the received signal 28 in the analogdomain and to convert its amplitude to a digital representation 29 forsubsequent digital signal processing (DSP) to decode the originaltransmitted data. In general, the sampling phase of the recovered clockthat samples the received signal affects the signal-to-noise ratio (SNR)in digital signal processing DSP, which in turn affects the receiverperformance. As illustrated in FIG. 2, the optimum sampling phase of apulse response is at the “Signal” point. Therefore, it is important forthe timing recovery system to regenerate a clock that is optimum inphase to sample the received analog signal.

Although many timing recovery designs have the same general phase lockloop structure shown in FIG. 1A, actual implementation of the phasedetector PD, loop filter LF, and voltage VCO or current controlledoscillator ICO can be very different for different applications. Asillustrated in FIG. 1B, one method of phase detection is by a methodcommonly called edge detection. In this detection scheme, the phasedifference 35 is simply determined by measuring the lag from the leadingedge 32 of a received data 34 pulse to the leading edge 36 of arecovered clock 38 pulse that is immediately after the data pulse.However, as illustrated in FIG. 2, when the received signal 41 suffersfrom a strong intersymbol interference (ISI) due to a band limitedchannel, a simple edge detection phase detector PD will fail, as thereceived signal has rising and falling slopes corresponding to precursorintersymbol interference ISI 42 and postcursor intersymbol interferenceISI 44 and therefore has no clear step transitions like those of squarepulses, and therefore no clear leading edges. One way to deal with thisproblem is to correlate the received signal with the detected output.From statistics, one can show that the correlation output between thetwo signals is a monotonic function of the phase difference between thedata transitions and the recovered clock. The correlation, thus, can beused in the phase detector PD to generate the phase error term. Thisapproach, known in the prior art, is commonly referred as theMueller-Muller (M&M) method and is illustrated in FIG. 3. In FIG. 3, thereceived signal 45 (having value r_(k)) and the detected signal (e.g.,the slicer output) 43 (having value a_(k)) are used for a computation bythe M&M method for phase detection given as follows.z _(k) =r _(k−1) a _(k) −a _(k−1) r _(k)Four DFF's (digital flip-flop) 46 in FIG. 3 are used to generate thedelay versions of the received signal 45 and detected signal 43. Thecomputation output (z_(k)) is sent to a loop filter (LF) 49 to driveVCO(or ICO) 48, which can be either voltage or current controlledoscillator. For those who are skilled in the art, the above equation canbe modified according to the statistics of the decoded output a_(k) andthe pulse respones shown in FIG. 2 so that the computation output(z_(k)) can generate a similar phase error term.

One critical limitation of the Mueller-Muller M&M method, however, isthat it requires correct detection of the original transmitted symbols(a_(k)), which in turn requires proper equalization adaptation to reducethe intersymbol interference ISI for correction detection. To remove orreduce intersymbol interference ISI for correct signal detection, atypical receiver 50, as shown in FIG. 4, includes both thefeed-forward-equalizer (FFE) 52 and decision-feedback-equalizer (DFE)54. A received (or incoming) signal 51 with ISI is processed by thereceiver 50. As used herein, the term “strong intersymbol interferenceISI” refers to intersymbol interference ISI that needs equalizationadaptation for signal detection. The result of this equalization is fedto a slicer 56, which detects the original transmitted amplitude fromthe input signal level. Since the channel impulse is unknown, bothequalizers 52, 54 need to be trained to more efficiently remove orreduce the ISI. A standard method of training the equalizer is calledstochastic least-mean-square (LMS) method. In brief, this methodcomputes the difference between the slicer 56 input and output, calledSlicer Error, and uses this error output to adapt the equalizercoefficients. The decoded slicer output 58 is fed to the Mueller-Muller(M&M) phase detector PD 57, whose output is in turn fed to a loop filter61, and passes to a voltage VCO (or current controlled oscillator ICO)62. This stochastic least-mean-square LMS training method, however, doesnot always work. One condition for the stochastic least-mean-square LMSmethod to be successful in training the equalizer is to sample thereceived signal at a good phase, which needs to be within a certainrange.

When intersymbol interference ISI is strong and before the equalizer isproperly trained, the decoded output may have many errors. As a result,the decoded output 58 fed to the Mueller-Muller M&M phase detector PD 57would not generate a correct phase error for clock recovery. Sincesuccessful equalizer training depends on good clock recovery, thechallenge for proper timing recovery and equalizer training becomes a“chicken-and-egg” problem, i.e., one needs good clock recovery to trainthe equalizer, but one also needs a trained equalizer to recover theclock.

Another limitation of the Mueller-Muller (M&M) method is that it doesnot provide information related to optimum phase sampling for maximizingthe signal detection performance. Although, as shown in FIG. 4, the M&Mphase detector PD 57 generates an output that is a monotonic function ofthe phase error, its zero crossing does not necessarily correspond tothe optimum phase that results in the maximum signal to noise ratio SNRin digital signal processing DSP. In fact, the zero-crossing location isdependent on the channel impulse response.

To solve the timing recovery problem in the presence of strongintersymbol interference ISI, several different schemes have beenproposed. In one method, a pre-cursor filter is introduced between theanalog-to-digital converter ADC 60 output and the feed forward equalizerFFE 52 input to shape the received waveform for Mueller-Muller M&M basedtiming recovery. In another method, a separate clock that runs at 8/7 ofthe symbol clock is used to present the timing recovery problem to aninterpolation problem of analog-to-digital converter ADC output samples.In both of these prior methods, the decoded output 58 from the slicer 56is still used to control the timing. Therefore, they are still subjectto the mutual dependence issue of the equalizer training and timingrecovery.

In yet another method of timing recovery, a separate analog-to-digitalconverter ADC 70 (not the one shown in FIG. 1 for signal detection) thatoperates at twice (2 times) of the symbol rate (or baud rate) is used(referred as 2×ADC). Symbol rate is the number of symbols per secondtransmitted, where each symbol is a modulated pulse that carries acertain number of information bits. For example, in the case of 10 Mb/sEthernet, the symbol rate is 10M (mega) symbols per second, and eachsymbol carries one bit. The data rate is 10 Mb/s. For gigabit Ethernet,the symbol rate is 125 MHz, and each symbol is a vector of four signals.That is, four parallel lines are transmitted inside a CAT-5 Ethernetcable. Each four-vector symbol together carries 8 information bits.Therefore, the total data rate is 1 gigabit per second. Intelecommunication terminology, symbol rate and baud rate are usedinterchangeably. That is, they mean exactly the same thing. On the otherand, symbol rate and data rate are different. The relationship can berepresented by: (data rate)=(symbol rate)×(net information bit carriedby each symbol). This method of timing recovery samples the receivedanalog signal 72 to generate two sample streams with their samplingphase difference by half of the symbol interval, as shown in FIG. 5. Inthis method, the received analog signal 72 is converted to digitalsignal by the 2×ADC 70 and is processed by the demultiplexer 74 into aneven stream 76 and an odd stream 78. A 2×ADC uses a sampling clock thatis twice of the symbol rate to sample the received signal stream and toconvert the analog signal to digital signal, whereas a 1×ADC uses asampling clock that is at the same symbol rate to sample a receivedsignal stream at the symbol rate to convert the signal from analog todigital format. As a result, a 2×ADC generates two samples from thereceived analog signal every symbol interval, and a 1×ADC generates onlyone sample every symbol interval. An even sample stream of a 2×ADC is asample stream from every other sample of the 2×ADC output, and an oddsample stream of the 2×ADC is a sample stream of samples that interleavewith the even sample stream. Therefore, the even and odd sample streamshave a sampling time difference of half of the symbol interval, and boththe even sample stream and the odd sample stream have one sample everysymbol interval. With these two streams of samples, as shown in FIG. 5A,autocorrelations R[0] and R[1] for each of these streams are computed bycalculator processor 80, 82 to generate a phase error output 84 fordriving the loop filter (LF) 86. Output from the loop filter 86 ispassed to a voltage or current controlled oscillator VCO 88, the outputof which goes back to the 2×ADC 70 for feedback. This method does notrequire input from either the equalizer output or the slicer output.Therefore, it avoids the need to have a correct detected output and canrobustly recover the clock. Once the clock is recovered, a delayedversion of the clock that maximizes R[0]-R[1] can be used to sample thereceived signal for DSP.

FIG. 5B illustrates a receiver 90 that incorporates the timing recoveryscheme of FIG. 5A. A separate 1×ADC analog to digital converter is usedto sample the received signal for equalizer training and signaldetection. An incoming analog signal 72 passes to the timing recoverysystem 92 according to the timing recovery scheme of FIG. 5A. A clocksignal 94 is recovered from the incoming signal and is delayed through adelay-tap logic (which includes delay select logic 96 and delay taps 98)for driving the sampling the 1×ADC analog to digital converter 100 toconvert the incoming analog signal 72. The digital output from the 1×ADC100 is sent through the equalizer 102 to the detector 104 to result inrecovered data 106. To train the equalizer, the output from the 1×ADC100 is processed through processor 108 to find the difference inautocorrelations R[0]-R[1] to determine the additional delay for thesampling clock 99 via the delay logic.

The method of FIG. 5A and FIG. 5B, however, still has limitations.First, it requires a separate ADC, i.e., it needs to have two ADC's(analog to digital converters) for processing one received signalstream—one 2×ADC to recover the clock and another 1×ADC to train theequalizers. The reason is that the sampling phase from the clockrecovery is not within the range for the equalizer to be trained.Therefore, a separate 1×ADC is required for actual signal detection, andits sampling clock has a certain delay from that of the recovered clock.The second limitation is that the 2×ADC used in clock recovery operatesat twice of the symbol rate (i.e., a 2×ADC is needed). This thusrequires higher speed implementation.

Thus, there is a need for a clock recovery technique and system in whichless demanding analog to digital converter systems are required.

SUMMARY

To overcome the limitations of prior data transmission systems, thepresent invention provides a new technique that recovers the clockdirectly from the received signal in the presence of a strongintersymbol interference ISI. Furthermore, it does not require twoseparate ADC's for processing a single incoming signal stream, i.e., notneeding one for timing recovery and one for signal detection. The reasonthat the need for a separate ADC can be avoided is that the samplingphase from timing recovery is automatically about optimum for receivedsamples in the subsequent digital signal processing DSP.

In one aspect, the present invention provides a data communicationdevice that includes a receiver for receiving and processing one or moreincoming signals, a timing recovery processor for recovering a clocksignal for sampling one or more of the incoming signals, and a detectioncircuit to recover original transmitted data from the receiver output.The receiver receives the signal with intersymbol interferencecomponents and produces resultant signals with less interference. Therecovered clock signal having a phase also being suitable for thereceiver to reduce the intersymbol interference components.

In another aspect, the present invention also provides a datacommunication device that includes N receivers for receiving andprocessing N incoming signals having intersymbol interference componentsto produce resultant signals with less interference (where N is aninteger bigger than 1), at least one first timing recovery processor forrecovering the clock signals for sampling the N incoming signals beforethe receivers are trained, detection circuits to recover originaltransmitted data from the N receiver output; and at least one secondtiming recovery processor for tracking the clock signals after thereceivers are trained. The receivers have equalizers that need to betrained to process the incoming signals according to the phases thereof.

The present invention also provides methods for data communication. Inone aspect, the method includes receiving one or more incoming signalsat a symbol rate and having intersymbol interference component andrecovering resultant signals with less interference. The method recoversresultant signals via recovering a clock signal for sampling the one ormore incoming signals. The clock signal is suitable for signal detectionof the incoming signals under strong intersymbol interference.

Because the present invention uses an analog-to-digital converterefficiently, less number of ADC is needed than in prior art datatransmission schemes. In one aspect, an ADC functions to recover a clockof the incoming signal, as well as samples the incoming signal at asuitable phase for the receiver to reduce the intersymbol interference.One embodiment of the technique of the present invention includes one2×ADC that operates at twice of the symbol rate when there is only onetransceiver in the system. A second embodiment of the new techniqueincludes one 1×ADC per transceiver to operate at the symbol rate whenthere is more than one transceiver in the system. In the secondembodiment, for example, two 1×ADC's operating at the symbol rate areused together and take turn to recover the timing(s) of the two signalstreams. Once timing is recovered for one signal, its correspondingreceiver can be trained for signal recovery to reduce the intersymbolinterference. When both receivers (for both signal streams) are trained,each receiver and its timing recovery will operate on its own, whereprior art methods that require only one ADC at the symbol rate fortiming recovery can be used.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates the basic baseband timing recovery structure.

FIG. 1B illustrates the implementation of phase detection using edgedetection.

FIG. 2 illustrates the ISI in a band limited digital communicationsystem.

FIG. 3 illustrates the prior M&M method.

FIG. 4 illustrates a typical receiver that removes ISI before signaldetection.

FIG. 5A illustrates a prior timing recovery scheme that uses a separate2×ADC for clock recovery.

FIG. 5B illustrates a prior receiver device with a timing recoveryscheme of FIG. 5A, showing a separate 1×ADC for signal detection.

FIG. 6 shows the block diagram of clock recovery of the presentinvention in a first embodiment when there is only one transceiver inthe system.

FIG. 7 shows the block diagram of clock recovery of the presentinvention in a second embodiment when there are more than onetransceiver in the system.

FIG. 8 shows the block diagram of an embodiment of optimum phaseselection in the embodiment of FIG. 7 of the present invention.

FIG. 9 shows the block diagram of an embodiment of optimum phaseselection in another embodiment of the present invention.

DETAILED DESCRIPTION OF INVENTION

The present invention provides a transceiver and timing recovery systemand technique in which only relatively inexpensive analog to digitalconverting systems are needed. As shown in FIG. 6, an embodiment of thetransceiver and timing recovery system 110 includes a 2×ADC,demultiplexer 114, a math processor 116, averager 118, loop filter 120,voltage or current controlled oscillator VCO (or ICO) 122. Theembodiment shown in FIG. 6 can be generally considered to include aclock signal recovery system 124 and a receiver 126 that includesfeed-forward-equalizer (FFE) 128, decision-feedback-equalizer (DFE) 130and slicer 132 wherein the equalizers FFE 128 and DFE 130 are trained toreduce strong intersymbol interference to result in the recovered signal133. A received signal 72 enters the system 110. The demultiplexer 114separates the 2×ADC output to an even and an odd-sample stream, one ofwhich is forwarded to the receiver 126. The math processor 116 uses theeven and odd-sample streams to compute an output according to EQ (1)below. The averager 118 averages the math processor output over acertain period of time.

As shown in FIG. 6, there is only one analog to digital converter ADC,i.e., the 2×ADC 112 for both timing recovery and signal detection. Thetiming recovery uses the 2×ADC 112 to compute a phase error signal todrive loop filter LF and voltage VCO (or current controller oscillatorICO) in clock recovery. Once timing recovery is done, one of the two ADCoutput streams coming off the demultiplexer 114 is fed to the receiver126 for equalizer training and transmitted data detection. Therefore,the same ADC is used for both timing recovery and signal detection. Inthis scheme, there is one received signal stream and only one ADC (the2×ADC 112) is needed to recover the clock and to train the equalizers.No M&M phase detector is needed. However, if desired, a different phasedetector PD can be included to enable continuing timing recovery oncethe clock is initially recovered by the scheme of FIG. 6. This can bedone by using the M&M PD to find the phase difference between the signalfrom the ADC (or from the FFE) and the detected signal from the slicer.

In further details, an aspect of the operation of the present inventionis described as follows. Let the two output streams from the 2×ADC bex_(k)=r(kT) and y_(k)=r(kT+0.5 T), respectively, where T is the periodof the symbol rate and k is an integer as an index to the samplingposition in the sampling order. For convenience's sake, let the firststream be referred to as the even stream, and the second stream bereferred to as the odd stream, and one lags behind the other by 0.5 T.These two streams were separated by the demultiplexer 114 and fed to themathematical processor 116.

With the above output streams from the 2×ADC, the mathematical processor(math block) 116 in FIG. 6 performs the following computations:z _(k)=(x _(k+1) −x _(k))(y _(k+1)−2y _(k) +y _(k−1))   EQ (1)Thus, the math block 116 takes the difference of two consecutive samplesof the even output stream of the ADC and multiplies it with thedifference of two end samples from twice the mid sample of threeconsecutive samples of the odd stream (lags the first stream by 0.5 T)from the same ADC. This computation output is taken average over aprogrammable period, e.g., over 8 to, for example, 512 or more, e.g.,2048 symbol clock cycles (typically in power of 2 to simplify actualhardware and software implementation). This averaging gives a periodicwaveform as a function of the sampling phase and has zero crossing at aphase optimum or close to optimum for training equalizers to recover thesignals. In other words, reducing z_(k) to zero leads to a phase optimumor about optimum for training equalizers to recover the signals.Obviously, other programming periods are applicable and can be easilyselected by one skilled in the art. This average output is input to aloop filter LF, which can then generate a voltage to drive the voltageor current controlled oscillator VCO/ICO to generate the recoveredclock.

Because the phase of the recovered clock from the phase lock loop in theclock recovery system 124 will result in a zero or close-to-zero valueat the output of the phase detection, use of EQ (1) for doing phasedetection will result in optimum or close-to-optimum sampling of thereceived signal for signal detection (i.e., the sampling phase resultsin successful equalizer training and maximum SNR for signal detection).With this property, there is no need for a separate ADC in doingequalizer training in addition to the ADC for timing recovery as shownin FIG. 5B.

One aspect of the present invention is the discovery of using EQ (1) fortiming recovery and for optimum phase sampling at the same time. Thereason EQ (1) used for phase detection can also result in the optimumsampling phase is described as follows.

For a received signal of the form: $\begin{matrix}{{r(t)} = {\sum\limits_{k}{A_{k}{h( {t - {kT}} )}}}} & {{EQ}\quad(2)}\end{matrix}$where A_(k) is the amplitude modulated output of the transmitted dataand h(t) is the pulse response of the transmission channel. Sampling thesignal at the symbol rate will result in a sampled output of the form:$r_{n} = {{r( {{nT} + \phi} )} = {{\sum\limits_{k = {- \infty}}^{\infty}{A_{k}{h( {{nt} - {kT} + \phi} )}}} = {\sum\limits_{k = {- \infty}}^{\infty}{A_{n - k}{h( {{kT} + \phi} )}}}}}$where φ is the sampling phase. With a delay of m symbol intervals, thetime averaged m-th autocorrelation is${R_{r}\lbrack m\rbrack} = {\frac{1}{N}{\sum\limits_{n = 0}^{N - 1}( {r_{n}r_{n + m}} )}}$From EQ (2), if each transmitted amplitude A_(k) is independent of A_(j)for k≠j, we can find that R_(r)[0]-R_(r)[1] is given by: $\begin{matrix}{{{R_{r}\lbrack 0\rbrack} - {R_{r}\lbrack 1\rbrack}} = {\frac{1}{2}{E\lbrack A_{k}^{2} \rbrack}{\sum\limits_{n = {- \infty}}^{\infty}( {h_{n} - h_{n + 1}} )^{2}}}} & {{EQ}\quad(3)}\end{matrix}$

This autocorrelation function is a periodic function of the samplingphase φ. The optimum phase for signal detection by training equalizersfor interference (noise) reduction is the phase that results in themaximum SNR at the input to the slicer for signal detection. One choiceof locating this optimum phase is to maximize the value ofR_(r)[0]-R_(r)[1]. Alternatively, one can locate the optimum phase bymaximizing the value of R_(r)[0]. In general, the two phases thatoptimize the values R_(r)[0]-R_(r)[1] and R_(r)[0], respectively, areclose to each other and can both be used as the sampling phase fortraining the equalizers and for signal detection. In the followingdiscussion, we use R_(r)[0]-R_(r)[1] as the criterion to locate theoptimum sampling phase. One who is skilled in the art, based on thepresent application, can use R_(r)[0] to derive a similar function fordoing the phase detection.

Since the sampling phase of the recovered clock from timing recovery inFIG. 5A at a steady state results in zero crossing at the phase detectoroutput, use of the same R_(r)[0]-R_(r)[1] function as the phasedetection function will not result in a maximum or close-to-maximumvalue of R_(r)[0]-R_(r)[1]. In the present invention, it is discoveredthat a different phase detection function whose zero crossing willresult in a maximum value of R_(r)[0]-R_(r)[1]. With this new function,the phase values that result in peak values at the phase detector outputwill result in a close-to-zero value for the autocorrelation functionR_(r)[0]-R_(r)[1], and the phase values that result in zero values atthe phase detector output will result in close-to-peak values ofR_(r)[0]-R_(r)[1]. The latter case is what is desired from timingrecovery to enable signal detection under strong intersymbolinterference.

According to the present invention, recognizing that R_(r)[0]-R_(r)[1]is generally sinusoidal, one can achieve a new phase detection functionthat has a 90° phase difference from that of EQ (3) by taking thederivative of EQ (3) with respect to the sampling phase φ. With this,the peak values of the new phase detection function andR_(r)[0]-R_(r)[1] have a shift of 90° in phase, and the zero crossing ofthe phase detection function corresponds to the peak value of EQ (3). Inother words, this new phase detection function will result in arecovered clock that has a 90° phase difference from that of FIG. 5A.Therefore, this new phase detection function can be used to recover aclock signal that is also suitable for sampling the incoming signalsunder strong inter-symbol interference. As a result, there is no need togenerate another signal of 90° phase difference from that of the clocksignal for optimal signal detection, as is needed in the scheme of FIG.5A. For this reason, an additional ADC is not necessary for equalizertraining in the present invention as the scheme of FIG. 5B needs.

Taking the derivative of EQ (3), we have $\begin{matrix}{{\frac{\partial}{\partial\phi}{\sum\limits_{n = {- \infty}}^{\infty}( {h_{n} - h_{n + 1}} )^{2}}} = {2{\sum\limits_{n = {- \infty}}^{\infty}{( {h_{n} - h_{n + 1}} )( {\frac{\partial h_{n}}{\partial\phi} - \frac{\partial h_{n + 1}}{\partial\phi}} )}}}} & {{EQ}\quad(4)}\end{matrix}$With this, one can take the following two steps to obtain the phasedetection function of EQ (1) as an approximation to EQ (4). First, usethe following approximations for the derivatives: $\begin{matrix}{\frac{\partial h_{n}}{\partial\phi} \approx \frac{h_{n + 0.5} - h_{n - 0.5}}{T}} & {{EQ}\quad(5)}\end{matrix}$

With this, if the transmitted symbol A_(k) given by EQ (2) isstatistically independent of other symbols (that is, the expectationvalue of A_(k)A_(j) is zero when k≠j), one who is skilled in the art canshow that EQ (1) is the desired phase detection expression for EQ (4).

Although EQ (1) is used in this disclosure, those who are skilled in theart can have a different equation to approximate EQ (5) and to generatea different phase detection function other than EQ (1). Furthermore, onewho are skilled in the art can have a modified equation to EQ (1) toapproximate EQ (4) when transmitted symbols A_(k) in EQ (2) are notcompletely independent.

With the new function given by EQ (1), its zero crossing with respect tothat of R_(r)[0]-R_(r)[1] given by FIG. 5A is shifted by 90 degrees. Asa result, the clock phase from the timing recovery coincides with theoptimum phase required for training the equalizers. Therefore, as shownin FIG. 6, one of the 2×ADC output streams (e.g. the even output) 127can be used to train the equalizers for signal detection.

In the second embodiment of the invention, shown in FIG. 7, there aremore than one receiver in the system that operate on the same clock.Therefore, only one timing recovery circuit is needed to recover theremote transceiver clock. Since we need to have two analog to digitalconverters ADC's to sample the two received signals, we can use two1×ADC (sampling the received signals at the symbol rate) to replace the2×ADC in the first embodiment. With this, the timing recovery and signaldetection process is described as follows. In this scheme, although weneed more than one ADC for signal detection and time recovery initiallyto train equalizers, only one ADC at the symbol rate is needed after theequalizers are trained. Therefore, with the arrangement disclosed below,only one ADC per input signal at the symbol rate is required. Although asystem of two receivers 134, 136 is described in this embodiment, it iscontemplated that the present invention can be extended to multiplereceived signal streams and still no more than one ADC per received(i.e., input) signal streams will be necessary to recover the clock andtrain the equalizers for signal detection.

In the embodiment of FIG. 7, during the first timing recovery, the firstreceived signal (“RX1”) 138 is fed to both ADC's 140, 142, which havethe sampling clocks with phase difference by half of the clock period.This clock delay can be achieved by a programmable delay logic. Receivedfirst signal RX1 138 is digitized (sampled) by the first ADC (which is a1×ADC) 140. Also, the first multiplexer 146, which can receive eitherincoming first signal (RX1) 138 or second signal (“RX2”) 144, selectsRX1 138 and directs it to the second ADC (which is a 1×ADC) 142 to bedigitized. Both digitized signals of RX1 138 from the two ADC's 140, 142are received by the Math block 148 and the averager 150, and furtherprocessed through loop filter 152 and voltage or current controlledoscillator 154 similar to what has been described above in FIG. 6 inclock recovery for obtaining the optimal sampling phase at the zerocrossing of EQ (1). The output from the math block 148 and the averager150 is sent to a second multiplexer 156. The second multiplexer 156during the first timing recovery selects it over another input from theM&M phase detector 158 (or other similar methods and will be discussedlater) and passes it to the LF 152 and the VCO 154 to generate therecovered clock. This recovered clock signal 160 is returned to thefirst ADC 140 to complete the loop. With this arrangement, the sametiming recovery method in the first embodiment of FIG. 6 can be used torecover the clock. The math block 148 performs EQ. (1) as describedabove, similar to the function performed by math block 116 in the schemeof FIG. 6.

Once the clock is recovered, we can use it to sample the first receivedsignal 138 as input to the first equalizer 162 (feed forward equalizer).Thus, the sampled signal 164 coming out from the first ADC 140 is sentto the first FFE 162 of the first receiver 134, with its ISI cancelledby the first decision feedback equalizer DFE 168, and decoded by thefirst slicer 166 to result in the first recovered signal S1 170.

Once the first feed forward and feedback equalizers are trained, thedecoded output S1 170 can correctly recover the transmitted data.Therefore, we can then use the M&M method or other prior art phasedetection method to perform the second timing recovery. Thus, the signalfrom the first ADC (which can, but not necessarily have to, pass throughthe equalizer) is processed by the M&M phase detector 158 (or otherequivalent detector) in conjunction with the decoded output signal S1170 to detect their phase difference. The M&M phase detectors PD's 158output is selected by the second multiplexer 156 during the secondtiming recovery to be processed through the loop filter LF 156 and VCO154 to recover the clock. A selection algorithm drives the method ofselection by the second multiplexer 156 to select between input from theaverager 150 and input from the M&M phase detector 158. When we switchthe timing recovery method, there is no need for the second samplestream from the second ADC 142. Therefore, we can use the second ADC 142to sample the second received signal RX2 144 as shown in FIG. 7. Here,for processing the second received signal RX2 144, the first multiplexer146 selects the RX2 144 and sends it to the second ADC 142. An algorithmdirects the first multiplexer 146 to select between RX1 138 and RX2 144at the proper time. The sampled, digitized signal from the second ADC142 is then sent through its own loop in the second receiver 136 toresult in the recovered second signal S2 174. The loop includes thesecond FFE 176, second slicer 178 and second DFE 180 in FIG. 7.

Before the second feed forward equalizer 176 and second feedbackequalizer 180 are to be trained in the second receiver, we need toselect a proper delay from the recovered clock to sample the secondreceived signal 144. To effect such a delay, for example, a programmabledelay logic 179 can be implemented by a simple shifted-delay line thatis well known in the art and is shown in FIG. 8. In this illustration,the VCO output 179 is input to the delay line input 208, fifteen delaytaps 181-195 are incorporated to introduce 16 delays over one clockinterval T, and one of the tap output is selected as the sampling clock210 for the second ADC 142 of FIG. 7. In practice, the number of tapdelays over one clock interval T can be larger to improve the resolutionof the optimum phase selection.

The criterion in choosing one of the tap output is described as follows.Once the multiplexier (MUX) 146 of FIG. 7 selects the second receivedsignal RX2 144 for the second ADC 142, the tap outputs are searchedsequentially or with other methods. For each tap selection, peakdetection is performed for the second ADC 142 output for a period oftime that is long enough to determine a peak in relation to the samplingphase. The interval for this peak detection could range, for example,from 32 clock cycles to 2048 clock cycles. The second ADC output 200 isprocessed by peak detection 202 and sequential/max peak selectioncontrol 204 to drive a clock selection multiplexer 206 to select thesignals from the clock input 208 and the taps 181-195 as the clockoutput 210. The tap selection that results in the maximum peak detectionvalue is selected as the final clock for the sampling clock for thesecond ADC 142, providing the desired sampling phase. This samplingphase that results in the maximum peak corresponds to the peak of thechannel impulse response illustrated in FIG. 2. Thus, the clock forrecovery of the signal with reduced ISI from the second received signalRX2 144 is obtained by a delay of the recovered clock of the firstreceived signal RX1 138 based on the phase difference of the tworeceived signals RX1138 and RX2 144.

The second embodiment of the invention can be extended to a system ofmultiple receivers that operate at clocks of different frequencies. Inthis case, the same method and arrangement is used to recover the timingof the first receiver and to train the first equalizer. Once the firstequalizer is trained, the equalizer parameters as a result from thefirst training are memorized. With this, the timing recovery andreceiver operation for the first receiver are temporarily stopped andthe first ADC is used together with the second ADC for the timingrecovery and equalizer training of the second receiver. Once bothequalizers are trained, prior art timing recovery methods such as theM&M method are used for each receiver, and the two receivers start tooperate independently. Such a system is shown in FIG. 9. The system hasa first timing recovery processor 228 for the first receiver—signalprocessor 238, which processes the first signal RX1 to reduce the ISIcomponents therein. A second timing recover processor 280 recovers aclock signal for the second receiver-signal processor 270, whichprocesses the second signal RX2 to reduce the ISI components therein.Equalizer training on the first signal RX1 can be done in the followingway.

The first signal RX1 is selected as the output 203 from Multiplexer 202.Signal 203 from RX1 is input to 1×ADC 210. The first VCO 222 output 243is selected as the output 205 from Multiplexer 230 as the sampling clockfor 1×ADC 210. RX1 is also selected as the output 253 from Multiplexer250. A delay of half of the sampling interval of VCO output 222 via aProgrammable Delay 242 is used as the sampling clock for the second1×ADC 252. Signal 253, at this time the RX1 signal, is used as the inputsignal to the second 1×ADC 252, which generates a sampled stream output255. Two sampled streams 207 and 255 from RX1 are the two signals usedin EQ (1) to perform timing recovery and equalizer training of the firstreceiver 238. When the first receiver 238 is trained with the firsttiming recovery processor 228, the equalizer coefficients of the firstreceiver and signal processor 238 are frozen or stored in memory. Whenthe coefficients are stored, RX2 training can begin.

Equalizer training on the second signal RX2 can be done in the followingway. The second signal RX2 is selected as the output 253 fromMultiplexer 250. Signal 253 (from RX2) is input to 1×ADC 252. The secondVCO 264 output 247 is selected as the output 251 of Multiplexer 246 asthe sampling clock for 1×ADC 252. RX2 is also selected as the output 203from Multiplexer 202. A delay of half of the sampling interval of VCO264 output 247 via a Programmable Delay 244 is used as the samplingclock for the first 1×ADC 210. Signal 203, which comes from RX2, is usedas the input signal to the first 1×ADC 210, which generates a sampledstream output 207. Two sampled streams 207 and 255 from RX2 are the twosignals used in EQ (1) to perform timing recovery and equalizer trainingof the second receiver 270. When the second receiver 270 is trained withthe second timing recovery processor 280, the equalizer coefficients ofthe second receiver-signal processor 270 are frozen or stored in memory.

After receivers 238 and 270 are trained separately, timing recoveryprocess which uses M&M process for time recovery (Method B) is switchedon, and the respective stored equalizer coefficients for the receivers238 and 270 are restored. In this case, their respective M&M output 209and 257 are used as the input to their respective loop filter LF 220 and262 for their respective timing recovery. The equalizer coefficients fortheir respective receivers are not changed or adapted until theirrespective sampling clocks of RX1 and RX2 is reestablished using timingrecovery Method B.

Embodiments of the present invention have been described withspecificity. It is to be understood that conventional circuitry,transmission devices, microprocessors, computers, and components andcombinations thereof, can be used for implementing the presentinvention. For example, microprocessors with the proper computer codeprogramming can be used for processing various computation or selectionblocks of the embodiments of the present invention, such as the Math andMethod blocks of, e.g., FIG. 6 and FIG. 7. Such computer codeprogramming is within the skill of one or ordinary skilled in the art.It is to be understood that various combinations and permutations ofvarious parts and components of the schemes disclosed herein can beimplemented by one skilled in the art without departing from the scopeof the present invention.

1. A data communication device, comprising: (1) a receiver for receivingand processing one or more incoming signals having intersymbolinterference components to produce resultant signals with lessinterference, (2) a timing recovery processor for recovering a clocksignal for sampling one or more of the incoming signals havingintersymbol interference components, the recovered clock signal having aphase also being suitable for the receiver to reduce the intersymbolinterference components; and (3) a detection circuit to recover originaltransmited data from the receiver output.
 2. The data communicationdevice according to claim 1 wherein the timing recovery processor has aphase detection function with which a phase value that results in peakvalues of the phase detection function will result in an about zerovalue for autocorrelation functions of an incoming signal, and the phasevalue that results in about zero value of the phase detection functionwill result in about peak value for the autocorrelation functions of theincoming signal.
 3. The data communication device according to claim 1includes at least one analog to digital converter (ADC), one of the atleast one ADC sampling an incoming signal for timing recovery, thedevice being capable of signal detection of the incoming signal understrong intersymbol interference and performing timing recovery with nomore than one ADC per incoming signal stream.
 4. The data communicationdevice according to claim 3 wherein the timing recovery processor has aphase lock loop including the ADC that samples the incoming signal fortiming recovery, wherein the sampling phase of the phase lock loopcauses the same ADC to generate a sample stream that achieves aboutoptimum performance for training an equalizer and signal detection.
 5. Adevice according to claim 3 wherein the incoming signal has a symbolrate and the timing recovery processor is adapted to recover a timingclock by a phase detector that multiplies two signals, the first onebeing a difference in value of two consecutive samples of a first ADCsampling output stream at the symbol rate, the second one being adifference in value of the sum of two end samples from twice the valueof the mid sample of three consecutive samples of a second ADC samplingoutput stream at the symbol rate, the first sample of the threeconcecutive samples of the second ADC sampling output stream leads thefirst sample of the two consecutive samples of the first ADC outputstream by half the period of symbol interval.
 6. A device according toclaim 3 wherein the timing recovery processor takes two output streamsfrom one 2×ADC for timing recovery and the receiver takes one of the twooutput streams from the 2×ADC to generate a signal output with lessintersymbol interference for signal detection, the samples of each ofthe two output streams are one symbol interval apart, and the two outputstreams have sampling phases one half of the symbol interval apart.
 7. Adevice according to claim 3 wherein the receiver has equalizers forprocessing an ADC output to reduce the intersymbol interferencecomponents for signal detection and wherein the timing processor takestwo output streams from two different 1×ADC's for timing recovery andthe receiver takes one of the two output streams from the ADC's fortraining equalizers for signal detection.
 8. A device according to claim5 wherein the timing recovery processor has an averager that averagesthe product from the multiplication.
 9. A device according to claim 3wherein the timing recovery processor has a phase lock loop includingthe ADC that samples the incoming signal for timing recovery, whereinthe sampling phase of the phase lock loop without any additional phasedelay causes the ADC to provide an output sample stream that achievesabout optimum performance for signal detection.
 10. A device accordingto claim 3 wherein the receiver includes equalizers for signal detectionand wherein the timing recovery processor can recover the timing priorto equalizer training even when the incoming signal has a strongintersymbol interference.
 11. A device according to claim 3 wherein thereceiver takes only one of the one or more incoming signals as the onlyinput for achieving signal detection.
 12. A device according to claim 3wherein the timing recovery processor achieves timing recovery and aboutoptimum phase sampling for the incoming signal for training an equalizerand signal detection.
 13. A device according to claim 5 wherein twodifferent 1×ADC's are used to process incoming signals to result in thetwo ADC sampling output streams each at the symbol rate.
 14. A deviceaccording to claim 5 wherein a 2×ADC is used to process incoming signalsto result in the two ADC sampling output streams each at the symbolrate.
 15. A data communication device, comprising: (1) N receivers forreceiving and processing N incoming signals having intersymbolinterference components to produce resultant signals with lessinterference, the receivers having equalizers that need to be trained toprocess the incoming signals according to the sampling phases thereof,where N is an interger bigger than 1, (2) at least one first timingrecovery processor for recovering the clock signals for sampling the Nincoming signals before the receivers are trained, such that the phaseof the recovered clock signals also being suitable for at least one ofthe N receivers to reduce the intersymbol interference components, (3)detection circuits to recover original transmited data from the Nreceiver output; and (4) at least one second timing recovery processorfor tracking the clock signals after the receivers are trained.
 16. Thedata communication device according to claim 15 wherein an ADC is firstused for processing a first incoming signal stream for clock recoverythereof and then used to process a second incoming signal stream toresult in a signal of the second incoming signal stream with reducedintersymbol inteference components.
 17. The data communication deviceaccording to claim 16 wherein a delay circuit delays a clock recoveredfrom the first incoming signal stream to result in a clock that drivesthe reduction of ISI from the second incoming signal stream.
 18. Thedata communication device according to claim 16 wherein a Mueller-Mullerphase detector is used to track the clock of a first incoming signalstream after equalizer training of a receiver for reducing ISI of saidfirst incoming signal stream.
 19. The data communication deviceaccording to claim 16 wherein the first incoming signal has a symbolrate and the ADC is used to generate the second sampling output streamin a phase detector that multiplies two signals, the first one being adifference in value of two consecutive samples of a first ADC samplingoutput stream at the symbol rate, the second one being a difference invalue of the sum of two end samples from twice the value of the midsample of three consecutive samples of a second ADC sampling outputstream at the symbol rate, the first sample of the three concecutivesamples of the second ADC output stream leads the first sample of thetwo consecutive samples of the first ADC output stream by half theperiod of symbol interval, each of the the first ADC and the second ADCsamples the first incoming signal.
 20. The data communication deviceaccording to claim 19 wherein the first ADC is adapted such that after afirst receiver has been trained to reduce the intersymbol interferencecomponents in the first signal the first ADC can be switched to recovera time clock for a second incoming signal, and the second ADC is adaptedthat it can be switched to process the second incoming signal after thefirst receiver has been trained on the first signal.
 21. The datacommunication device according to claim 19 wherein no 2×ADC and no morethan N 1×ADC's sampling at the symbol rate are used in the device.
 22. Amethod for data comunication, comprising: receiving one or more incomingsignals at a symbol rate and having intersymbol interference componentand recovering resultant signals with less interference, via recoveringa clock signal for sampling the one or more incoming signals, the clocksignal being suitable for signal detection of the incoming signals understrong intersymbol interference.
 23. The method according to claim 22comprising timing recovery and recovering resultant signals with no morethan one analog to digital converter (ADC) per incoming signal.
 24. Themethod according to claim 22 comprising using the same ADC forrecovering a resultant signal and for timing recovery.
 25. The methodaccording to claim 22 comprising using two different ADC's forrecovering two resultant signals and for timing recovery.
 26. The methodaccording to claim 22 comprising recovering timing clock signal bymultiplying two signals, the first one being a difference in value oftwo consecutive samples of an output stream of a first 1×ADC, and thesecond one being a difference in value of the sum of two end samplesfrom twice the value of a mid sample of three consecutive samples ofanother output stream from a second 1×ADC, the first sample of the threeconcecutive samples of the second 1×ADC leads the first sample of thetwo consecutive samples of the first ADC by half the period of a symbolinterval.
 27. The method according to claim 22 comprising recoveringtiming clock signal by multiplying two signals, the first one being adifference in value of two consecutive samples of a first output streamof a 2×ADC, and the second one being a difference in value of the sum oftwo end samples from twice the value of a mid sample of threeconsecutive samples of another output stream from the 2×ADC, the firstoutput stream and the second output stream of the 2×ADC have a samplingtime difference of half of the symbol interval, and the first sample ofthe three concecutive samples of the second 1×ADC leads the first sampleof the two consecutive samples of the first ADC by half the period of asymbol interval.
 28. The method according to claim 22 comprising using aphase lock loop for timing recovery, the phase lock loop including anADC that samples the incoming signal for timing recovery, wherein thesampling phase of the phase lock loop causes the ADC to provide anoutput sample stream that achieves about optimum performance for signaldetection.
 29. The method according to claim 22 comprising using a phasedetection function with which a phase value that results in peak valuesof the phase detection function will result in an about zero value forautocorrelation functions of an incoming signal, and the phase valuethat results in about zero value of the phase detection function willresult in about peak value for the autocorrelation functions of theincoming signal.
 30. The method according to claim 22 comprising using aphase lock loop including an ADC that samples the incoming signal fortiming recovery, using a phase detection function for phase sampling inthe phase lock loop such that the sampling phase without any additionalphase delay causes the ADC to provide an output sample stream thatachieves about optimum performance for signal detection.
 31. The methodaccording to claim 22 comprising determiningz _(k)=(x _(k+1) −x _(k))(y _(k+1)−2y _(k) +y _(k−1)) as a function forphase detection where k is the sampling position in the samplingsequence, x and y are output streams of the same signal after analog todigital conversion, where x_(k)=r(kT) and y_(k)=r(kT+0.5 T), and T isthe period of the symbol rate.
 32. The method according to claim 31comprising switching to use a different phase detection function forcontinued timing recovery after a clock signal has been recovered withthe z_(k)=(x_(k+1)−x_(k))(y_(k+1)−2y_(k)+y_(k−1)) phase detectionfunction and the intersymbol interference components are reduced. 33.The method according to claim 22 comprising using an ADC first forprocessing a first incoming signal stream for clock recovery thereof andthen to process a second incoming signal stream to result in signal ofthe second incoming signal stream with reduced intersymbol inteferencecomponents.
 34. The method according to claim 22 comprising delaying aclock recovered from a first incoming signal stream to result in a clockthat drives the reduction of ISI from the second incoming signal stream.35. The method according to claim 22 comprising using a Mueller-Mullerphase detector to track the clock of a first incoming signal streamafter training equalizers of a receiver for reducing ISI of said firstincoming signal stream.
 36. The method according to claim 22 comprisingusing a first ADC and a second ADC to recover a time clock for a firstincoming signal and train a first receiver to reduce intersymbolinterference components in the first incoming signal and then use thefirst ADC and the second ADC to recover a time clock for a secondincoming signal and train a second receiver to reduce intersymbolinterference components in the second incoming signal.
 37. A transceiverfor data comunication, comprising code means for taking a sampled signalfrom an incoming signal and determining a sampling phase suitable forequalization adaptation at about optimum performance for signaldetection.
 38. The transceiver according to claim 37 comprising codemeans for recovering timing clock signal by multiplying two signals, thefirst one being a difference in value of two consecutive samples of afirst ADC output stream, and the second one being a difference in valueof the sum of two end samples from twice the value of a mid sample ofthree consecutive samples of a second ADC output stream, the firstsample of the three concecutive samples of the second ADC output streamleads the first sample of the two consecutive samples of the first ADCoutput stream by half the period of symbol interval.
 39. The transceiveraccording to claim 37 comprising code means for a phase detectionfunction with which a phase value that results in peak values of thephase detection function will result in an about zero value forautocorrelation functions of an incoming signal, and the phase valuethat results in about zero value of the phase detection function willresult in about peak value for the autocorrelation functions of theincoming signal.